The invention relates to a method of, and a circuit arrangement for, digitally transferring bit sequences in selective manner between a higher-order circuit part and a lower-order circuit part. Taking over English language usage, one often speaks of master and slave in conjunction with higher-order and lower-order circuit parts. The term host also is commonly employed for the higher-order circuit part. In practical embodiments, the master circuit part may be a microcontroller and the slave circuit part may be a function block having function means such as control means and measuring means.
The master circuit part and the slave circuit part usually cooperate via a bus system by means of which digital signals can be transferred between the master circuit part and the slave circuit part. The signal transfer via the bus system is subject to a defined protocol, which is frequently referred to as bus protocol.
A known bus system is the so-called SPI (Serial Peripheral Interface) with the associated SPI bus protocol. This is shown, for example, in the data sheet of the company Aureal Semiconductor, relating to circuit VSP 901, pages 12 and 13, dating from February 1997.
The signal representation shown in FIG. 7 of said publication is depicted herein in attached FIG. 13. In this figure:
SCK is the serial clock
HREQ is the host request signal
SS is the slave select signal
MOSI is the Master Out Slave In (transfer from master to slave)
MISO is the Master In Slave Out (transfer from slave, to master)
SPICMD is an additional signal that extends the SPI protocol to indicate whether the master has placed a register address or register data on the SPI bus.
Some operating features of the SPI bus protocol will now be discussed briefly by way of FIG. 13.
Signal HREQ has a logic value L (LOW) when the master is ready to receive a 24-bit data word. The slave is connected to the master via a slave select line SS. Via these slave select lines, the host informs the slave when it intends to send the particular data information to the slave. The respective data word is transferred via the MOSI lines from the host or master to the slave, and a data word transmitted before is transferred back to the master or host via the MISO line. Upon occurrence of the first clock pulse of the next data word to be transferred, HREQ is set to logic value H (HIGH) by the master. The master scans SPICMD and sets HREQ to H when it is ready to receive the next data word. If SPICMD is L, this indicates the transfer of a register address. If SPICMD is H, this indicates the transfer of a register value. The host deactivates the SS line after it has written the last bit to the master. In case the host deactivates the SS line of the receiving master before the end of the data word transfer since the host has to settle first a task of higher priority, the data word transfer is aborted and the master discards the received data.
FIG. 12 shows in a block circuit diagram a circuit arrangement suitable for the SPI protocol, comprising a master circuit part e.g., in the form of a microcontroller xcexcC, a serial interface SI and a slave circuit part in the form of a multi-function block MFB accommodating e.g., six functions F1 to F6. The functions F1 to F6 in total require, for example, a data field having a data field width or data bit number of 30. A data bus DB connecting the serial interface SI and the multi-function block MFB thus has a corresponding data field width of 30 bits. The microcontroller xcexcC and the serial interface SI are connected to each other via three terminals: a serial input Sin, via which serial bit sequences can be transferred from microcontroller xcexcC to serial interface SI, a serial output Sout, via which serial bit sequences can be transferred from serial interface SI to microcontroller xcexcC, and a clock terminal CLK, via which a system clock can be supplied to serial interface SI.
In a data transfer, the data for all functions F1 to F6 must be transferred each time. Thus, a data transfer with a data width of 30 bits is necessary each time. When a function needs to be reprogrammed, writing over of all functions FB1 to FB6 is necessary. This involves the risk that functions whose programming actually is to remain unchanged are erroneously programmed in a different manner.
The SPI protocol involves some problems.
1. When during transfer from master to slave a data value is corrupted, the corrupted or falsified data value is written to the target register of the slave, without the master being informed of whether a correct or an incorrect data transfer has taken place.
2. When a data value is corrupted within a slave, the master is not notified thereof. To overcome this problem, an examination (which is not provided for in the SPI protocol) of the entire reading back operation and a new write operation would have to be carried out. This would consume operating time of the master and delay the entire data transfer.
3. The SPI protocol uses a fixed data word length. Each bit within this fixed data word length has a specific function. When one of the master or slave is altered with respect to one or parts of its functions, all functions have to be programmed anew, also the functions that are not to be altered. This means that also the functions not requiring new programming have to be written over. This increases the risk of erroneous programming changes.
4. In case one or several functions are to be added later on, this necessitates as a rule a hardware change. The interface between master and slave is designed for the fixedly determined data word length, which in the example shown in FIG. 12 is a data word length of 30 bits. If, by adding additional functions, an increase in the data word length becomes necessary, both the interface and the process control will have to be changed.
The present invention has the object of overcoming such problems. In particular, more flexibility with respect to functional changes and extensions of functions as well as increased safety as regards a correct data transfer are to be achieved.
The invention to this end makes available a method and a circuit arrangement, which can be developed in advantageous manner in accordance with the description herein. In addition thereto, a test bit generator is provided, which is of significance both for the method and for the circuit arrangement.
The method provides a bus protocol for digitally transferring bit sequences in selective manner between a master means and several selectively controllable slave means via an interface means provided therebetween, making use of bit sequences of predetermined maximum frame length, comprising an address field addressing the respective slave means to be controlled, a control field containing control information, and a data field. While the address field and the control field each have a predetermined field length or bit number, the data field for the slave means may have different field lengths or data bit numbers as long as the data field does not exceed a (freely selectable) maximum data bit number. The bit sequences transferred in serial form are written in succession to successive register stages of an interface register and read back to the master means. Reading back is carried out register stage for register stage immediately after having been written to the respective register stage where writing to a register stage and reading back from this register stage take place during the same clock pulse. The master means compares the bit read-back from the respective register stage with the bit transmitted for this register stage. When the read-back memory contents of any of the register stages are not in conformity with the bit transmitted from the master means for this register stage, the master means blocks the transfer of the respective transmitted bit sequence to the respective addressed slave means.
This method ensures that a bit read incorrectly to the interface register is immediately recognized as incorrect, and that clock errors, for example the omission of one or more clock pulses, are recognized. In case of a corrupt bit sequence, this sequence is not transferred first to the addressed slave means as the corruption becomes evident only during examination after transmission of the entire bit sequence, but rather the transfer to the addressed slave means is not released at all when the bitwise examination, reveals an error in the respective bit location read to the interface register.
According to the invention, each of the individual functions has a slave means of its own associated therewith. The individual slave means can be addressed separately and can make use of various data field lengths.
The data field length associated with a specific slave means can be accommodated in the address code for this slave means. The respective address then indicates to the master means how big the data field length of the addressed slave means is and when a bit sequence end signal can be set. When new slave means are added, the data field length thereof is encoded in the address thereof. It is thus possible without a problem to add new slave means with arbitrary data field lengths as long as these data field lengths are below the maximum data field length established for the entire system. When particularly high flexibility is to be retained, the maximum data field length can be set to a high value so that further slave means requiring high data field lengths can still be added later on. This does not necessitate a hardware change as regards the master means, the interfaces or the process control.
Particularly simple is coding of the data field length within the addresses when the individual addresses have assigned thereto spaces or locations within a predetermined address sequence in an address register, with a specific data field length being associated to the location of a specific address within the address sequence.
In a preferred embodiment of the invention, the control field of the bit length to be transferred has the length of one bit only. The control bit of a bit sequence transmitted from the master means provides information as to whether a write or a read operation is to be carried out. When an error is detected during an operation in which data bits are to be transferred from the master means to a slave means, said detection being made with the aid of a direct reading back of the bits written to the individual register stages of the interface register, the control bit of the bit sequence transmitted from the master means is used for blocking reading of the bit sequence written to the interface register into the addressed slave means.
In the bit sequences transferred from the slave means to the master means, the control bit can be used for delivering status information to the master means. This may provide information as to whether the data contents of the respective addressed slave means have changed since the last write and/or read operation for this slave means, be it due to a data corruption or new existing data, for example since the slave means is a sensor or measuring means.
In another embodiment of the invention, the control bit (optionally all control bits) in a bit sequence transmitted from the master means is separated therefrom, and only the address field and the data field are passed on to the slave means. The control information obtained from the control bit is sent via separate signal lines to the slave means. In case of a transfer of a bit sequence from a slave means to the master means, a control bit (or several control bits), for example in the form of the status bit mentioned, is introduced into this bit sequence before the bit sequence reaches the master means.
For generating a status bit for the master means, an embodiment of the invention provides for a test bit generation in which a test bit is generated from a bit sequence transferred between the master means and a slave means, and is stored. During the next transfer of a bit sequence between the master means and the same slave means, another test bit is generated and compared with the previously stored test bit. From this comparison, a status bit is generated by means of which the master means is notified whether or not the data contents of the slave means concerned have changed since the previous transfer of a bit sequence between the two.
Test bit storing advantageously takes place in a test bit register within the respective slave means.
A circuit arrangement according to the invention comprises an interface register and a conversion means disposed between the master means and the interface register. This conversion means may comprise a process control means and a multiplexer. Control signals obtained by means of the process control means can be used on the one hand for taking out the control bits of the respective bit sequence or inserting them thereinto, and on the other hand can be used to control the bitwise writing of the serial bit sequence obtained from the master means to the individual register stages of the interface register as well as to control reading back of the memory contents of the individual register stages of the interface register in the master means. Between conversion means, interface register and slave means, there may be connected a switching unit which, in accordance with the write/read information obtained from the master means, passes the bit sequence written to the interface register both back to the master means and to the slave means, or passes the bit sequence read from an addressed slave means to the master means.
Test bit generation preferably makes use of a series connection of a plurality of XOR elements. The first XOR element of this series connection is fed with the first and second bits of the bit sequence to be tested. The additional XOR elements are fed with a further bit of the bit sequence and an output signal of the respective preceding XOR element. The test bit is available at the output of the last XOR element.
In a further development of this test bit generator, the last XOR element of this series connection is followed by an additional XOR element which on the one hand is fed with the respective actual or current test bit and on the other hand with the stored, preceding test bit and at the output of which an information signal is available which provides information as to whether the respective bit sequence examined has changed between the times of preceding test bit generation and current test bit generation. The output signal of the additional XOR element can thus be used as a status signal which may be introduced as a control bit into a bit sequence to be transferred to the master means.
This type of test bit generator is significant both in connection with the inventive protocol in the form of the method according to the invention and the circuit arrangement according to the invention as well as independently thereof. Such a test bit generator, independently of the protocol according to the invention, may be used wherever a test bit is to be produced for bit sequences, possibly together with an additional generation of a change information signal.
The invention as well as additional objects, aspects and advantages of the invention and of embodiments thereof will now be discussed by way of examples with reference to the drawings in which: